LteRlcUmRxEntity

Package: simu5g.stack.rlc.um

simple module LteRlcUmRxEntity

LTE (TS 36.322) receiving side of the Unacknowledged Mode (UM) of the RLC layer: FI-walk reassembly across concatenated PDUs with a PDU-SN reordering window and a t-Reordering timer. Shares the common RlcUmRxEntityBase shell (MAC-mux plumbing, D2D hooks, UL burst-throughput accounting) with the NR profile NrRlcUmRxEntity. Bound by default inside the LteRlcUmEntity compound. Its throughput/delay statistics are emitted on the sibling rlcMux module (see RlcMux).

simu5g.stack.rlc.um.LteRlcUmRxEntityLteRlcUmRxEntitysimple

Inheritance diagram

Known subclasses

Name

Type

Description

LteRlcUmRxEntityD2D

simple module

D2D-capable LTE (TS 36.322) RLC UM receiving entity: LteRlcUmRxEntity plus the D2D_MULTI single-PDU reordering window, the post-mode-switch reassembly resynchronisation, and the D2D branch of the throughput/delay statistics.

Parameters

Name

Type

Default value

Description

macModule

string

“^.^.mac”

Set by the enclosing RlcUmEntityBase compound (per leg)

rlcMuxModule

string

“^.^.rlcMux”

This bearer’s leg mux; set by the RlcUmEntityBase compound

timeout

double

1s

Timeout for RX Buffer

rxWindowSize

int

16

PDU reorder window

Properties

Name

Value

Description

display

i=block/layer

dynamic

true

Gates

Name

Direction

Size

Description

in

input

PDUs from MAC, via the RlcMux

out

output

Reassembled SDUs to the PDCP layer (direct per-DRB connection, not via a mux)

Signals

Name

Type

Unit

Description

rlcDelayDl

rlcDelayUl

rlcPduDelayDl

rlcPduDelayUl

rlcPduThroughputDl

rlcPduThroughputUl

rlcThroughputDl

rlcThroughputUl

Statistics

Name

Title

Source

Record

Unit

Interpolation Mode

Description

rlcDelayDl

Delay at the rlc layer DL

rlcDelayDl

mean

s

rlcDelayUl

Delay at the rlc layer UL

rlcDelayUl

mean

s

rlcPduDelayDl

PDU delay at the rlc layer DL

rlcPduDelayDl

mean

s

rlcPduDelayUl

PDU delay at the rlc layer UL

rlcPduDelayUl

mean

s

rlcPduThroughputDl

PDU throughput at the rlc layer DL

rlcPduThroughputDl

simu5g_rateavg

Bps

rlcPduThroughputUl

PDU throughput at the rlc layer UL

rlcPduThroughputUl

simu5g_rateavg

Bps

rlcThroughputDl

Throughput at the rlc layer DL

rlcThroughputDl

simu5g_rateavg

Bps

rlcThroughputUl

Throughput at the rlc layer UL

rlcThroughputUl

simu5g_rateavg

Bps

Source code

//
// LTE (TS 36.322) receiving side of the Unacknowledged Mode (UM) of the RLC
// layer: FI-walk reassembly across concatenated PDUs with a PDU-SN reordering
// window and a t-Reordering timer. Shares the common RlcUmRxEntityBase shell
// (MAC-mux plumbing, D2D hooks, UL burst-throughput accounting) with the NR
// profile ~NrRlcUmRxEntity. Bound by default inside the ~LteRlcUmEntity
// compound. Its throughput/delay statistics are emitted on the sibling rlcMux
// module (see ~RlcMux).
//
simple LteRlcUmRxEntity like simu5g.stack.rlc.IRlcRxEntity
{
    parameters:
        @dynamic(true);
        @display("i=block/layer");
        string macModule = default("^.^.mac");  // Set by the enclosing RlcUmEntityBase compound (per leg)
        string rlcMuxModule = default("^.^.rlcMux");  // This bearer's leg mux; set by the RlcUmEntityBase compound
        double timeout @unit(s) = default(1s);            // Timeout for RX Buffer
        int rxWindowSize = default(16);                   // PDU reorder window


        //# Per-bearer statistics. A bearer serves one peer, so these are already
        //# per-UE; aggregate over a UE's bearers in the analysis tool.
        @signal[rlcDelayDl];
        @statistic[rlcDelayDl](title="Delay at the rlc layer DL"; unit="s"; source="rlcDelayDl"; record=mean);
        @signal[rlcThroughputDl];
        @statistic[rlcThroughputDl](title="Throughput at the rlc layer DL"; unit="Bps"; source="rlcThroughputDl"; record=simu5g_rateavg);
        @signal[rlcDelayUl];
        @statistic[rlcDelayUl](title="Delay at the rlc layer UL"; unit="s"; source="rlcDelayUl"; record=mean);
        @signal[rlcThroughputUl];
        @statistic[rlcThroughputUl](title="Throughput at the rlc layer UL"; unit="Bps"; source="rlcThroughputUl"; record=simu5g_rateavg);
        @signal[rlcPduDelayDl];
        @statistic[rlcPduDelayDl](title="PDU delay at the rlc layer DL"; unit="s"; source="rlcPduDelayDl"; record=mean);
        @signal[rlcPduThroughputDl];
        @statistic[rlcPduThroughputDl](title="PDU throughput at the rlc layer DL"; unit="Bps"; source="rlcPduThroughputDl"; record=simu5g_rateavg);
        @signal[rlcPduDelayUl];
        @statistic[rlcPduDelayUl](title="PDU delay at the rlc layer UL"; unit="s"; source="rlcPduDelayUl"; record=mean);
        @signal[rlcPduThroughputUl];
        @statistic[rlcPduThroughputUl](title="PDU throughput at the rlc layer UL"; unit="Bps"; source="rlcPduThroughputUl"; record=simu5g_rateavg);

    gates:
        input in;       // PDUs from MAC, via the RlcMux
        output out;     // Reassembled SDUs to the PDCP layer (direct per-DRB connection, not via a mux)
}

File: src/simu5g/stack/rlc/um/LteRlcUmRxEntity.ned